1. Field of the Invention
The present disclosure relates to flat panel display technology, and more particularly to a method for compensating resistance of signal lines of gate driving circuits and the liquid crystal panel applying the same.
2. Discussion of the Related Art
LCDs typically are characterized by attributes including thin, power-saving, and low radiation. These are reasons that the LCDs have been widely adopted by devices, such as mobile phones, personal data assistant (PDA), digital cameras, monitors for personal computers or notebooks.
Most of the LCDS are backlight-type devices, including a housing, a liquid crystal panel and a backlight module arranged within the housing. Conventional liquid crystal panel includes a color filter, a Thin Film Transistor Array Substrate (TFT Array Substrate) and a liquid crystal layer disposed between the two substrates. The operating principle relates to applying a driving voltage to the two glass substrate to control the liquid crystal alignment within the liquid crystal layer such that the light beams from the backlight module are reflected to generate images. Thus, the backlight module is one key component of LCDs. Backlight module may be divided into two categories, including edge-type and direct-lit backlight, according to the incident location of the light source. With respect to the direct-lit backlight, the Cold Cathode Fluorescent (CCFL) Lamp or the Light Emitting Diode (LED) is arranged behind the liquid crystal panel, which forms a surface light source for the liquid crystal panel. With respect to the edge-type backlight, the LED bar is arranged on the edges of the back plate disposed behind the liquid crystal panel. The light beams emitted from the LED light bar enters the light guiding plate (LGP) from a light incident surface of the LGP, and the then reflected and diffused within the LGP. Afterward, the light beams emit out from a light emitting surface of the LGP, and then pass through an optical film set so as to form the surface light source for the liquid crystal panel.
Gate driving on array (GOA) technology has been commonly adopted recently for manufacturing narrow border or frameless products. The limited space may result in the resistances of the signals line are not qualified, or are deviated from desired values.
FIG. 1 shows a GOA dual-driven panel. The control board system connects to the TFT via flexible printed circuits (FPC) to provide a variety of signals. The length of the four pull-lines of the clock signals, which are arranged on the pull-line area, are different. CK4 is the longest one and CK1 is the shortest one, which may result in that the RC delay of CK4 is larger than that of CK1. As R4C4>R3C3>R2C2>R1C1, the four signal lines have different initial waveforms when entering GOA. As shown in FIG. 2, the waveforms of CK4 through CK1 changes in sequence. It can be seen that the RC delay of the waveform of CK4 is the largest one, and that of CK4 is the smallest one. That is, the waveform of CK1 is the best one.
Most of the time, the RC delay of the clock signals of GOA have to be the same as the clock signals are Gate signals inputted to the active area (AA). Gate signals are for turning on TFTs arranged on the pixels arranged on one horizontal row such that the source signals charges the pixel electrode. The difference between the RC delays of two clock signals may result in different gate delay, also different charging state. At this moment, the gray scale of the two adjacent pixel rows with different charging rate may be different. As such, users may see horizontal bright-and-dark fringes, and this may become more obvious while the signals are passed downward along with shift registers.